where
Seattle, Washington. I moved up from Spokane after wrapping up at Gonzaga; the rack came with me, the bench is rebuilt, the workflow is settling.
what i'm working on
The MWSCAS 2026 paper on NeuroMatrix is submitted and under review. Most of my research time right now is going into the things I deferred to get the paper out — and the biggest of those is Fabrica.
Specifically: Section 5 of the Fabrica codebase — EKV-to-PSP consistency tests, the cross-tier validation work that proves the three-tier verification story actually holds across all three engines. The Rust IR bindings are the other half of the same push; the Circuit IR has to round-trip cleanly between the C++ solver core and the Python user surface before any of the consistency machinery is meaningful. Both are in flight; both are the kind of work that pays back tenfold once finished and zero until it is.
The EN-59 sensor board is in Itron's manufacturing queue with boards expected in hand in June. When they arrive, bring-up takes over — power-on, JTAG, PGA gain step characterization, deep-sleep current measurement against the sub-2 µA target. Evenings turn into bench work for at least a month after that.
Ensemble is in maintenance mode rather than active development. The platform serves its 650+ orgs without daily attention; the next real push is membership-level sync from the Neon v2 API, which I chip at on weekends when nothing on the research stack is blocking.
what's next
I'm not applying to graduate programs this cycle. The plan looked clean on paper a few months ago — ETH, Stanford, UW, Georgia Tech, TU Delft — and I walked it back deliberately. NeuroMatrix and Fabrica are still pre-tape-out; the work that would make a graduate application actually distinctive is the work I'd be applying to do, and the better version of that conversation happens in a year when there's silicon on the table. I'd rather defer than apply from the weaker position.
Industry-side: not actively interviewing, but open to hear from people. If you're hiring for CPU validation, DV, analog or mixed-signal design, or anything where the work involves real silicon and honest verification, I'd like to talk. I'm especially interested in roles where the engineering culture treats verification as first-class work rather than a downstream cost center.
not doing
Not starting any new projects until after the EN-59 boards are validated and Fabrica Section 5 closes. Not pretending to be available for things I'm not. Not writing as much as I want to. Not getting enough sleep.